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Operational Amplifiers & Feedback Systems

1. Op-Amp Fundamentals​

The Operational Amplifier (Op-Amp) is the fundamental building block of analog electronics. It is a high-gain, DC-coupled voltage amplifier with a differential input and usually a single-ended output.

Ideally, an op-amp takes the difference between its two input voltages (V+ and V-), multiplies it by a massive Open Loop Gain (AOL), and outputs the result. However, because this gain is so high (often >100,000), the op-amp is rarely used alone. Instead, we use Feedback to tame this gain and force the op-amp to perform precise mathematical operations like addition, integration, and filtering.

Key Characteristics:

  • Active Component: It requires power to operate.
  • Feedback Dependent: The external components (resistors, capacitors, diodes) determine the circuit's function, not the op-amp itself.
    • Example: A capacitor in the feedback loop creates an Integrator (frequency-dependent).
    • Example: A diode in the feedback loop creates a Precision Rectifier (non-linear).

Ideal vs. Real Behavior:

  • Ideal Output: A perfect voltage source (0Ω output impedance). It maintains the target voltage regardless of load current.
  • Real Output: Limited by current drive capability.
  • Ideal Input: Infinite impedance (draws 0 current).
  • Real Input: Draws tiny bias currents (nA to pA range).

The Golden Rules​

When analyzing op-amp circuits with negative feedback, two simple rules allow you to solve almost any schematic:

  1. The Voltage Rule: The output will do whatever is necessary to make the voltage difference between the two inputs zero (V+ = V-).
  2. The Current Rule: The inputs draw no current (I+ = I- = 0).

Inverting Amplifier​

  • Input impedance is R1, since point A is ground.
  • Issue: Its very low input impedance = R1.
  • Output: 180 degrees out of phase.

Image Source: The Art of Electronics

Example & Derivation:

  • Following Golden Rule 1: Input B is at ground, Input A is also at ground. So VR1 = Vin.
  • And VR2 = Vout.
  • Following Golden Rule 2: The op-amp input gets no current, so the current through R1 equals the current through R2.
    • Vin / R1 = - Vout / R2
  • From this it follows that Gain = - R2 / R1.

Non-Inverting Amplifier​

Analysis: Both inputs have to equal each other, so VA = Vin.

  • So if Vin increases, so will point A, so the output will increase.
  • Point A is set by the voltage divider, so if you increase R2, then the division is larger, the output will have to compensate and increase the output even more to make Vin = VA.
  • R1 and R2 are attenuators. Which means they reduce the input signal's magnitude by a set ratio to prevent saturation.

Image Source: The Art of Electronics

These circuits can work as either inverters or unity gain amplifiers dependent on switch.

Image Source: The Art of Electronics

Voltage Follower (Buffer)​

Configuration: This is a special case of the Non-Inverting Amplifier where the feedback resistor is a short circuit (R2 = 0Ω) and the input ground resistor is open (R1 = ∞).

  • Gain: Unity (1).
  • Math: Vout = Vin.

Image Source: The Art of Electronics

(Impedance Transformation) Even though it has no voltage gain, it provides massive Power Gain.

  1. High Input Impedance: It draws almost zero current from the source, so it doesn't "load down" or distort weak sensors.
  2. Low Output Impedance: It can supply significant current to drive heavy loads.
  3. Result: Isolates a fragile source from a demanding load.

2. Feedback Theory​

Feedback is the process of putting a fraction of the output signal (voltage or current) as an input by stabilizing one or the other by one of the following methods:

Mixing Methods​

1. Series Mixing (Voltage Subtraction)

  • You connect the feedback voltage in series with the input source.
  • The Circuit: The loop contains the Source, the Feedback Element, and the Amplifier Input.
  • The Math: Verror = Vsource - Vfeedback.
  • Result: This "inputs" a voltage.

2. Shunt Mixing (Current Subtraction)

  • You connect the feedback path in parallel (shunt) with the input source at a single node.
  • The Circuit: The source current, feedback current, and amplifier input current all meet at one junction.
  • The Math: Ierror = Isource - Ifeedback.
  • Result: This "inputs" a current.

Negative Feedback: If that output signal (Verror or Ierror) is opposite in value or phase, then it is negative feedback (or degenerative feedback). This opposes or subtracts from the input signal giving stabilization. For example, if the output changes for any reason, then the negative feedback counteracts that change.

The Feedback Correction Cycle (Detailed Analysis)​

Let's look at a Non-Inverting Op-Amp circuit.

Image Source: The Art of Electronics

  • Input Vin: +2V.
  • Divider (β): A resistor divider feeds 50% of the output back to the inverting input (V-).
  • Steady State: Output is +4V. Feedback (V-) is +2V. The Op-Amp sees 0V difference.

The Scenario: If open-loop gain suddenly increases, or the load changes, causing the output voltage to drift UP to +4.1V.

1. Steady State

  • Target: We want 4V output from a 2V input (Gain = 2).
  • Reference (V+): Fixed at 2.00000V.
  • Feedback (V-): The resistor divider creates a fixed link (V- = 0.5 × Vout). The Op-Amp drives the Output to 4V specifically so that this 50% fraction equals the 2V reference.

2. The Error Creation

  • Something (maybe a load change) forces the output to drift up to 4.1V.
  • The resistor divider transmits 50% of this drift to the Feedback pin V-.
  • New State: V- = 2.05V.
  • Error Calculation: The Op-Amp internally subtracts the inputs:
    • Verror = V+ - V- = 2.00V - 2.05V = -0.05V

3. The Reaction

  • The Op-Amp multiplies this negative error by its massive Open Loop Gain = 100,000.
  • Internal Drive: -0.05V * 100,000 = -5,000V.
  • The internal transistors violently pull the output voltage DOWN towards the negative rail to satisfy this request.

4. The Correction

  • As the Output drops 4.1V → 4.0V, the Feedback voltage V- also drops from 2.05V → 2.00V.
  • The Error shrinks towards zero.
  • The Internal Drive reduces from 5,000V towards reasonable levels.

5. Equilibrium

  • The Output does not stop when V- is exactly 2.00000V. If it did, the Error would be 0V, and the Output would collapse to 0V.
  • The system stops slightly "short" of perfection.
  • Final State:
    • Output: 4.0V
    • Reference (V+): 2.00000V
    • Feedback (V-): 1.99996V
  • The Math: The inputs maintain a tiny Residual Error of 40μV.
    • Vout = Error * Gain = 0.00004V * 100,000 = 4V.

Conclusion: The feedback loop creates a continuous stalemate. It maintains a tiny, non-zero error at the inputs just large enough to generate the drive required to hold the output steady.

3. Bandwidth & Stability​

Bandwidth and "Why?"​

What is Bandwidth? Bandwidth is the frequency range (in Hertz) over which the amplifier can maintain a constant gain. Outside this range, the internal transistors cannot switch fast enough, and the signal amplitude drops (attenuates).

Why Feedback improves Bandwidth (The Gain-Bandwidth Product): Real amplifiers act like "Low Pass Filters." They have massive gain at DC, but the gain drops off linearly as frequency increases.

  • Open Loop: You might have a gain of 100,000 up to 10Hz, but at 10kHz, the available gain might drop to only 100.
  • Closed Loop: You use feedback to forcefully clamp the gain to 10.
    • At 10Hz, you throw away 99,990 of the available gain.
    • At 10kHz, you still have 100 available gain, so you can easily maintain your target of 10.
    • At 100kHz, the open loop gain might finally drop below 10.

Result: By lowering the gain requirement, you extend the frequency range where the amplifier can physically keep up. You trade Gain for Bandwidth.

Closed Loop Gain: 40 dBBandwidth: 10.0 kHz
0 dB20 dB40 dB60 dB80 dB100 dB120 dB1Hz1kHz1MHzFrequency (Hz)Gain (dB)

Impedance Improvements​

Negative feedback also has effects of reducing distortion, noise, and sensitivity to external changes as well as improving system bandwidth and input/output impedances.

Why Feedback improves Output Impedance: Feedback tries to keep output voltage constant. If a heavy load (low resistance) tries to pull the output voltage down, the feedback loop detects the drop and drives the amplifier harder to compensate. This makes the output "stiff" (which is the definition of Low Output Impedance).

Feedback is unilateral, so it only travels in one direction (output to input). So the loop gain of the system is independent of the load and source impedance.

Gain Stability​

This is purely mathematical.

  • Let A = Transistor/Op-Amp Gain (Open Loop). This varies wildly with temperature (e.g., 10,000 +/- 50%).
  • Let B (β) = Feedback Factor (Resistor Divider). This is constant (e.g., 0.1).
  • The formula for Closed Loop Gain (ACL) is: ACL = A / (1 + A * B)

If A is very large (e.g., 100,000), then A * B is huge compared to 1. The formula simplifies: ACL is approximately A / (A * B) = 1 / B

The "Why": Since A cancels itself out, the gain depends only on B (the resistors). Since resistors are temperature stable and precise, the gain is stable, even if the transistor gain A changes by 50%.

4. Specific Circuit Configurations​

Transimpedance Amplifier (Current to Voltage)​

Simple Current to voltage converter.

  • Virtual Ground: Because the non-inverting input is grounded, the op-amp wants the inverting input to act as grounded. This is a Virtual Ground.
  • No Input Current: Because of the Golden Rule, the inverting input draws no current (ideally).
  • Current Path: So when the photodiode conducts and releases a current, it all flows through the feedback resistor Rf.
  • The Output Logic: The output voltage is then set to Id × Rf because the op-amp needs the inverting input to stay at ground. (The voltage drop across Rf determines Vout).
  • Result: This is a transimpedance amplifier. You are converting an input current into an output voltage.

Image Source: The Art of Electronics

Why use an op-amp in the first place?

  1. Capacitance Issue: Photodiodes have a capacitance. If you connected the photodiode directly to a resistor, you would create an RC filter by accident, reducing your bandwidth (limiting how fast you can detect light flashes).
  2. Voltage Issues: You can't put the photodiode in parallel with a resistor, because a voltage would form across the diode. You can't put it in series, because a large load resistor would limit your output drive because the resistance is so big.
  3. The Fix (Virtual Ground): The op-amp introduces a Virtual Ground. This isolates the photodiode capacitance from the resistor voltage swing. The capacitance doesn't have to charge/discharge with the signal voltage (since the node stays effectively at 0V), letting you operate faster without worrying about RC time constants.
  4. Output Impedance: The op-amp provides a very low output impedance, letting you drive subsequent stages easily.

The Stability Fix: An issue with real photodiodes is that their capacitance can still cause a phase delay in the feedback loop, leading to oscillation.

  • The Fix: Adding a small capacitor in parallel with Rf compensates for that delay.

Single-Ended Emitter Follower Booster (Figure 4.25)​

Figure 4.25 demonstrates a method to increase output current capability using an external NPN bipolar junction transistor (BJT) configured as an emitter follower.

Image Source: The Art of Electronics

Using an Op-Amp with an Emitter Follower

  • Output Drive: The output of the op-amp drives the base of the transistor, providing the necessary base current to control the transistor. This means the op-amp controls a large current (at the emitter) with the little current it can actually provide.

  • The Feedback Loop:

    • The inverting input needs to become equal to the non-inverting input.
    • You set your gain to 10 (1 + 10k/1.1k).
    • The output must match this, so if you input 2V, you would expect a 20V output at the load.
    • You need to compensate for the 0.7V transistor drop, so the op-amp output voltage pushes to 20.7V.
    • The emitter output becomes 20V.
    • The inverting input sees 2V (20V * 1.1k / (1.1k + 10k)), which balances the loop.

Why use an op-amp here?

  • Hiding the Drop: This hides the 0.7V drop from the transistor; the load gets exactly what you intended.
  • Drift Correction: This also hides any variations in the required VBE due to temperature changes.

Limitation (Sourcing vs. Sinking): The circuit in Figure 4.25 is a single-ended stage using an NPN transistor.

  • Sourcing: It can actively supply current out of the emitter to a load returned to ground or a negative voltage.
  • Sinking: It cannot sink current into the output from a load. If the load requires current to flow into the output terminal, the NPN transistor turns off.
  • This configuration is suitable only for applications where the output voltage is always positive relative to the load return.

The Push-Pull Solution and Crossover Distortion​

To handle AC signals or loads that require both sourcing and sinking current, a complementary "push-pull" stage is needed (mentioned as Figure 4.26 in the text). This utilizes an NPN transistor to source current and a PNP transistor to sink current.

Image Source: The Art of Electronics

Crossover Distortion: In a basic push-pull stage, there is a "dead zone" around zero volts output where neither transistor is conducting (the NPN needs +0.7V VBE to turn on; the PNP needs -0.7V VBE). As the signal crosses zero, the op-amp must rapidly slew its output voltage across this ~1.4V gap to activate the other transistor.

Slew Rate Limitation: The op-amp has a finite slew rate (maximum rate of voltage change, dV/dt). At high frequencies, the op-amp cannot traverse this dead zone instantly, resulting in a period where the output does not track the input. This is called crossover distortion.

Feedback Compensation: Instead of using complex biasing schemes, the negative feedback loop actively corrects the error:

  • The Dead Zone (0V): During the zero-crossing, both the NPN and PNP transistors are off. The input is 0V, and the output is 0V.
  • The Error: When the input signal rises slightly to 0.1V, the inverting input needs to be 0.1V to satisfy the Golden Rule. However, it can't be, because the NPN transistor hasn't turned on yet (it needs 0.7V).
  • The Jump: The op-amp detects this error (Input = 0.1V, Feedback = 0V). It amplifies this error massively and instantly jumps its output voltage up to ~0.8V (0.1V + 0.7V).
  • The Fix: This jump instantly turns the NPN transistor on. The emitter output rises to 0.1V, and the inverting input matches the non-inverting input again. The "dead zone" is effectively skipped.

Push-Pull Detailed Analysis (Closed Loop Linearization)​

1. The Circuit Configuration and Goal The circuit uses an op-amp configured as a unity-gain non-inverting voltage follower to drive a push-pull BJT output stage.

  • Goal: The objective is to produce a perfect, undistorted replica of the input sine wave across the 10Ω load, despite the inherent nonlinearity of the push-pull stage.
  • Nonlinearity: The push-pull stage has a "dead zone" or crossover region where the input voltage must change by approximately 1.4V to switch from turning on one transistor to turning on the other.

2. Incorrect Feedback Point (Open-Loop Behavior) If the feedback is taken from the op-amp's output pin instead of the final load output:

  • Op-Amp Output: The op-amp output becomes a perfect sine wave, matching the input.
  • Load Output: The load sees the input signal minus the VBE drops. This results in severe crossover distortion, as the output voltage stalls near zero while the input swings through the ±0.7V dead zone. The op-amp is "unaware" of the distortion occurring after its feedback point.

3. Correct Feedback Point (Closed-Loop Linearization) When the feedback is taken from the final push-pull output (where the load is connected), the op-amp's task changes.

  • Op-Amp Task: The op-amp must now drive its own output pin to whatever voltage is necessary to force the final load voltage to match the input signal.
  • Compensation Mechanism: As the input signal crosses zero, the op-amp detects that the load output is lagging (due to the dead zone). The op-amp immediately slews its output voltage rapidly across the 1.4V dead zone.

Resulting Waveforms:

  • Op-Amp Output: The op-amp's output waveform becomes highly distorted and exaggerated. It exhibits sharp, nearly vertical jumps at the zero-crossing points to overcome the dead zone instantly.
  • Load Output: Because the op-amp has pre-compensated for the dead zone, the final output across the load becomes a clean, linearized sine wave that accurately tracks the input.

Filters & Differential Amps​

Filters:

  • Circuit 1: High pass filter into a non-inverting amplifier. DC can't pass into the non-inverting input. AC signals amplified.
  • Circuit 2: DC is gained off to 1, unity gain. Because DC can't see C1, it can't see R1 either, gain turning into R2/infinity + 1 = 1. Otherwise AC acts as usual.

Image Source: The Art of Electronics

Differential Amplifiers:

  • Important to have the input resistance be very close in value to achieve high CMRR.
  • Circuit B lets you select what the output is and what the ref should be to do special things instead of it being onto the op amp exactly.
  • The output is usually unity gain, you gain it out with other stages.
  • The output is just the difference between the 2 signals.

Image Source: The Art of Electronics

5. Current Sources​

1. Basic Current Source​

  • Vin is input, feedback sets inverting input equal to it.
  • That current that flows has to be Vin/R because inverting input HAS to be equal to Vin. So the current drawn is dependent completely on Vin and not the load whatsoever.
  • If R were to change, inverting input would change, output will compensate that with a higher voltage leading to the same current being drawn as before to get the inputs to the same value.
  • Note: Built just like a non-inverting amplifier btw.

Image Source: The Art of Electronics

2. More Complex Current Source (High Side Monitor)​

  • R1 and R2 set the reference voltage for the non-inverting pin. This is what the inverting pin will be set to.
  • The inverting pin is connected to the emitter of the PNP, so it'll have a 0.7V increase over the output.
  • The op-amp will make its output equal to Vin - 0.7V, so that the inverting input is at Vin.
  • Voltage on top of R is VCC, at the bottom its at Vin. So current flowing through R is (VCC - Vin) / R.

Image Source: The Art of Electronics

Issues:

  1. There is a bit of an issue where the current calculated doesn't take into account the base current draw, since some of it will go into the base, so not a perfect formula.
  2. The amount of waste varies because of the Early effect. When VCE changes, Beta shifts, changing IB, so the amount of waste can vary.
    • Fix: A Darlington pair can fix it because beta is so high, the slight jiggle doesn’t matter much at all.
    • Fix: Or just use a MOSFET. No current draw. Be careful of input capacitance. That input capacitance causes a delay in the feedback loop, moving it out of phase, which can make the output unstable and oscillate.

Flaw: Circuit has a flaw where the input voltage is a reference to VCC. But if you wanted an external voltage to control the current flow you would need something a bit different.

3. Second Current Source Example (Two-Stage / MOSFET)​

  • Here your input voltage goes into IC1.
  • Inverting pin of IC1 goes to your emitter of the BJT. Output of IC1 drives the base to Vin + 0.7V, which makes the inverting input equal to Vin. A current is drawn with I = Vin / R1.
  • This causes a voltage drop at the collector equal to VCC - (Vin / R1 * R2), which is at the non-inverting input of IC2.
  • IC2 then drives the gate of the P-MOSFET, allowing current to flow from VCC through R3 out the drain which is Iout.
  • The source voltage (top of the FET) is fed back to inverting input stabilizing R3 and R2.

Image Source: The Art of Electronics

Important Note: When working with OP-amps, do not assume that it will work close to the supply voltage without explicit consent of the datasheet.

6. Circuit Forensics Algorithm​

When you see a tangle of resistors, transistors, and op-amps that you don't recognize, you don't need to memorize every topology in the book. You just need to execute a standard Forensics Procedure.

Here is the 4-step algorithm to crack any unknown Op-Amp circuit, specifically for Current Sources.

Step 1: Verify Negative Feedback (The "Is it stable?" Check) First, trace the path from the Op-Amp Output. Does it eventually wiggle its way back to the Inverting Input (-)?

  • Yes: It is an Amplifier or Regulator. Proceed to Step 2.
  • No (or goes to +): It is a Comparator, Schmitt Trigger, or Oscillator. Stop analyzing for linearity; look for switching thresholds.

Step 2: Find the "Command" (The Target) 🎯 Look at the Non-Inverting Input (+). Whatever voltage is sitting on this pin is the "Law." The Op-Amp will destroy itself trying to force the Inverting Input (-) to match this voltage.

  • Ask: Is this voltage fixed (like a Zener/Reference) or variable (like a signal)? This tells you if the output is meant to be Static (DC Source) or Dynamic (Amplifier).

Step 3: Find the "Sense" Resistor (The Translator) 🗣️ This is the key for Current Sources. Look at the Inverting Input (-). It must be connected to a resistor that goes to a reference point (usually Ground or a Supply Rail). This is the Sense Resistor (Rsense).

  • The Logic: The Op-Amp monitors the voltage at the top of this resistor.
  • Since Rule I says V- = V+, the Op-Amp is forcing a specific Current through this resistor to create that voltage drop.
  • The Golden Formula: I_locked = V_Command (from Step 2) / R_Sense (from Step 3)

Step 4: Find the "Actuator" (The Muscle) 💪 Look at the Op-Amp Output. What is it driving?

  • Directly to Feedback: It's a simple Op-Amp circuit.
  • To a Transistor Base/Gate: The Op-Amp is using a "helper" to handle high current or high voltage.
  • To the Load: The Op-Amp is driving the load directly.

7. Capacitors in Op-Amps​

Think of that capacitor as a "Speed Limit" for the amplifier. Here is the breakdown of the three main reasons you see a capacitor across Rf (the feedback resistor), ranging from "Stability" to "Math."

1. The Stability Fix (The "Anti-Oscillator") This is the specific reason mentioned in the photodiode text you just read.

  • The Problem: Sensors (like photodiodes) have internal capacitance. This creates a time delay (lag) in the feedback signal. If the lag gets too big, the Op-Amp gets confused, chases its own tail, and starts screaming (oscillating).
  • The Capacitor Fix: By putting a small capacitor (e.g., 10pF) across Rf, you create a "Fast Lane" for high frequencies. It allows the high-frequency feedback to bypass the resistor and get to the input instantly, cancelling out the delay caused by the sensor.
  • Result: The oscillation stops. This is called "Compensation."

2. The Noise Filter (The "Silencer") This is common in audio and sensor circuits.

  • The Physics: A capacitor acts like a short circuit at high frequencies.
  • The Circuit Action:
    • At Low Frequencies: The capacitor is open. The feedback is just Rf. The Gain is High.
    • At High Frequencies: The capacitor shorts out Rf. The feedback path becomes "zero resistance."
  • Result: When the feedback resistance drops to zero, the Gain drops to zero (or unity).
  • Why do this? If you are measuring a slow temperature change (DC), you don't want to amplify radio waves, microwave interference, or high-pitched "hiss." The capacitor kills the gain for those fast signals, effectively creating an Active Low-Pass Filter.

3. The Practical Integrator (The "Leak" Stopper) You mentioned the Integrator having one. This is actually the reverse situation!

  • Ideal Integrator: Has ONLY a capacitor in the feedback loop.
  • The Problem: At DC (0Hz), a capacitor is an open circuit. That means there is no negative feedback at DC. The Op-Amp gain goes to infinity (Open Loop), and the output drifts until it slams into the power rail (Saturation).
  • The Resistor Fix: In a real integrator, we put a large Resistor (Rf) in parallel with the capacitor. This gives the DC bias currents a path to flow. It puts a "limit" on the DC gain so the Op-Amp doesn't drift into saturation.

Image Source: The Art of Electronics

Summary: If you see a capacitor in parallel with the feedback resistor:

  • Is it tiny (pF)? It's likely for Stability (preventing oscillation).
  • Is it medium (nF)? It's likely a Low-Pass Filter (killing noise).
  • Is the Resistor huge (MΩ)? It's likely a Practical Integrator (the resistor is just there to keep the DC stable).

Integrator Calculation: See Figure 4.16. With an input voltage of 1V DC, your output voltage will decrease by -Vin / RC. If R = 1M, C = 1μF, that's -1V per second decrease. A switch can be used to bypass the capacitor. This is done to reset the integrator since the op-amp will wander off since theres no feedback for DC.

8. Power Supplies & Non-Linear Circuits​

Power Supplies: Op-amps can provide gain for a feedback voltage regulator by comparing the output to a zener reference.

Image Source: The Art of Electronics

Comparators:

  • Compares its 2 input signals.
  • Simplest form is a differential amplifier with no feedback. It'll either saturate either negative or positive depending on the input voltages.
  • There are special ICs that allow you to select the comparison voltage, independent of the supplies.

[Image of Op Amp Comparator Circuit]

Schmitt Trigger:

  • Help with signals that either transition very slowly, or are noisy so that when they pass through a threshold, it happens many times. This is fixed with positive feedback.
  • Hysteresis: Output depends on input voltage and recent history.

[Image of Schmitt Trigger Circuit]

Comparators and Schmitt triggers can be used to instantly turn on/off loads.

Op-Amp Rectifiers: Rectification with small signals can't be done with diodes because of the 0.6V drop or 1.2V drop.

Image Source: The Art of Electronics

  • For Vin positive, the diode provides negative feedback, and for Vin negative, the op amp saturates to ground.
  • Op amp follower for lower output impedance.
  • Issues: Issues occur at high speeds because op amps can't switch fast enough so recovery from saturations hinders switching.

Circuit Detail: D1 makes the circuit a unity-gain inverter for negative input signals. D2 clamps the op-amp’s output at one diode drop below ground for positive inputs, and since D1 is then back-biased, Vout sits at ground.

9. Active Filters​

Sallen-Key Filter​

Normal filters have a soft roll-off, meaning the response versus frequency is not a sharp end in their passband and stopband. The Sallen-Key topology improves this.

Image Source: The Art of Electronics

Analysis of a Second Order Low-Pass:

  • The Circuit: This particular one is a second-order lowpass filter.
  • The Bootstrap (C1): C1 acts as a bootstrap capacitor to the output.
    • High Frequencies: The output is obviously zero (shorted to ground by the low-pass action), meaning C1 is grounded like normal. It acts like a standard capacitor shunting signal to ground.
    • Low Frequencies: When you decrease the frequency, C1 reduces the attenuation because it is getting biased from the output. Since the output follows the input (Unity Gain), the voltage across C1 is nearly zero, effectively "bootstrapping" it out of the circuit.
  • Result: Therefore, the change in signal is a lot sharper (higher Q-factor) near the cutoff frequency compared to a passive RC filter.
Filter Orders & Roll-Off

"Normal filters have a soft roll off..."

  • 1st Order (Passive RC): Rolls off at 20dB/decade (6dB/octave).
  • 2nd Order (Sallen-Key): Rolls off at 40dB/decade (12dB/octave). By using positive feedback (bootstrapping), the Sallen-Key topology allows you to create a "corner" that is much sharper than a passive filter, maximizing the flat passband before diving into the stopband.

10. Detailed Op-Amp Behavior​

Ideal vs. Real​

The Ideal Op-Amp has the following characteristics (Theoretical Model):

  1. Input Current = 0: Infinite input impedance.
  2. Vout = 0V: When both inputs are the same (Zero Offset).
  3. Output Impedance = 0: It can drive any load.
  4. Infinite Voltage Gain: Open loop gain is ∞.
  5. 0 Common Mode Voltage Gain: It strictly amplifies the difference, ignoring the shared voltage.
  6. Instant Output Change: Infinite Slew Rate.
  7. No Added Noise: Perfectly silent.
  8. Stability: All of these being independent of temperature and supply voltage.

11. Input Imperfections (DC Errors)​

Input Offset Voltage (Vos)​

The inputs are not perfectly balanced internally.

  • The Issue: If you were to connect the 2 input leads together (0V difference), the output would likely saturate to a rail. The offset is not perfectly 0V.
  • The Fix (Trimming): Some op-amps have a trimming lead (or "Null" pins) that you can use to offset the internal current mirror to get a perfect 0V offset using a potentiometer.

Offset Voltage Drift: Input offset voltage can drift varying with temperature and time.

  • Relevance: This is more important in Precision Amplifiers, since their "whole schtick" is having low offset voltage. If it drifts, you lose that precision.

Input Current & Bias Current (Ib)​

The inputs sink/source some bias current Ib.

  1. The Effect: This causes a voltage drop across resistors in the feedback network, bias network, or source impedance.
  2. Design Limit: This limits how large your resistors can be.
    • The Math: V_error = Ib * R. If R is huge, even a tiny bias current creates a massive voltage error at the input.

Input Offset Current (Ios)​

The input currents flowing through the leads is ideally 0, but there is of course some flowing.

  • The Imbalance: The current flowing through the inputs is unequal.
  • The Result: When driven by identical source impedances, the op-amp will see unequal voltage drops, which means a voltage difference between the inputs (an artificial differential signal).
Mitigating Bias Current

"Mosfet op-amps would have very low output voltages..."

  • BJT Inputs: Draw significant base current (nA to μA range).
  • FET/CMOS Inputs: Draw almost zero current (pA range). If your design uses high-value resistors (MΩ range), you must use a JFET or CMOS op-amp to avoid massive bias current errors.

Design Example: The 10mV Panel Meter​

Source: Adapted from The Art of Electronics

To see these errors in action, imagine designing a high-impedance DC amplifier for a sensitive voltmeter.

  • Goal: Measure ±10mV full-scale.
  • Specs: Gain = 100, Input Impedance = 10MΩ.

The Trap (Using a Standard Op-Amp like LF411):

  1. Offset Error (VOS): You short the inputs to calibrate zero, but the meter reads 2mV (a massive 20% error!).
    • Cause: The op-amp has a 2mV internal Input Offset Voltage.
  2. Drift Error (TCVOS): You trim the offset to zero using a potentiometer. You leave it in the sun, it warms up by 10°C, and now reads -0.2mV.
    • Cause: The offset drifts with temperature (20μV/°C).
  3. Bias Current Error (IB): You disconnect the test leads (open circuit). The meter suddenly jumps to +2mV.
    • Cause: The 200pA input bias current has nowhere to go but through your 10MΩ input resistor.
    • Math: 200pA × 10MΩ = 2000μV (2mV phantom voltage).

The Solution:

  • Precision FET Op-Amp: Use a part like the OPA336. Its bias current is only 10pA (negligible error across 10MΩ), and VOS is a tight 125μV.
  • Chopper (Auto-Zero) Op-Amp: For near-perfect performance, use a "Chopper" amp like the LTC1050. It actively measures and subtracts its own errors hundreds of times a second, achieving VOS < 5μV.

12. Input Ranges​

Common Mode Input Range (CMIR)​

Inputs to an op-amp have to stay within their range of operation.

  • If you exceed this (e.g., pulling inputs above VCC or below Ground), the internal transistors may saturate or invert phase (Phase Reversal), causing the output to snap to the wrong rail.

Differential Input Range​

This is the biggest difference allowed at the input pins.

  • Usually ranges from the source voltages.
  • Warning: Some bipolar op-amps have anti-parallel diodes between inputs. If you pull inputs apart by >0.7V, current will flow between the inputs, potentially destroying the chip.

13. Dynamic Limitations​

Slew Rate​

Slew Rate limits the speed at which the op-amp output can change (measured in Volts per microsecond, V/μs).

  • Slew rates can depend on the compensation network used inside the chip.
  • If a signal is too fast (high frequency + high amplitude), the output turns into a triangle wave because it can't "slew" fast enough to track the sine wave.

Capacitive Loading​

Look into capacitive loading in op-amp circuits.

  • The Problem: Capacitive loads (CL) interact with the op-amp's output impedance to create a pole.
  • The Result: This causes phase lag inside the feedback loop. If the lag hits 180 degrees, the negative feedback becomes positive feedback, and the circuit oscillates.

Fixing Capacitive Instability:

  1. Isolation Resistor: You can add a series resistor to the output, outside the feedback loop (e.g., 50 Ohms).
    • Trade-off: This means the feedback is not acting on the actual output signal (the load), but the resistor influences it instead (voltage drop across the resistor).
  2. Gain Adjustment: You can reduce the closed-loop gain to regain stability (allows for more phase margin).
  3. Datasheet Check: Certain op-amps state stability in certain capacitance ranges (e.g., "Stable with C_load > 1uF").
  4. In-Loop Compensation: Adding a unity gain buffer inside the feedback loop.
    • Caution: If you do that, you need to worry about phase shift introduced by the buffer. It should have a higher bandwidth than your op-amp.

14. Design Considerations​

Finite Loop Gain Effects​

Inverting Amplifier Design:

  • Closed loop gain is always lower than open loop gain.
  • Gain begins to drop as you leave the bandwidth of the op-amp.

Impedance Effects: Finite loop gain also affects input and output impedance.

  • Voltage Feedback: The open loop output impedance is lowered by a factor of 1 + AB.
  • Frequency Dependence: The output impedance will rise as frequency increases (kind of like an inductor) because the Gain (A) drops, so the divider 1 + AB gets smaller.
    • Eventually, gain goes back to unity (because you're out of the bandwidth).
    • Warning: Have to be careful because you can accidentally make an LC resonant circuit if the load is capacitive and the output impedance looks inductive.
  • Current Feedback: You want the output impedance to be very high. Feedback acts as an output impedance raiser.

Offset & Bias Management​

Offset Voltage: When both inputs are grounded, you can see an output because of this.

  • Solution 1: If you don't need DC gain (audio), use a capacitor in series with the input resistor. This drops DC gain to unity, so you don't amplify the offset.
  • Solution 2: Trim the voltage offset using the manufacturer's recommended trimming network.
  • Solution 3: Use a better op-amp with smaller Vos.

Input Bias Current: Even if you perfectly trim to get Vos = 0V, you will still get some kind of output because of the finite input bias current.

15. Single Supply Op-Amps​

There are op-amps that can operate with just one supply (e.g., +5V and GND, instead of +15V and -15V).

  • Benefit: Used to simplify some designs and save a lot of space like not needing a negative voltage reference.
  • Definition: In this case, the negative supply rail is considered ground.

Virtual Ground (The "DC Offset" Trick): In order to combat circuits in which the output wants to swing negative (AC Audio) because the input is centered on ground:

  1. You could add a reference voltage (VCC/2 as an example).
  2. Consider that "Virtual Ground" to get the swinging action.
  3. Note: You would need to bias each stage if there are multiple.

Image Source: The Art of Electronics

Supply Splitter:

  • Can also make a supply splitter.
  • By grounding the reference output, you split the single supply into a negative and positive pair (relative to that new center ground).

Image Source: The Art of Electronics

16. Instrumentation Amplifiers​

  • These are specialized differential amplifiers with settable voltage gain (usually via a single external resistor).
  • Key Specs: Very high stability and very high CMRR (Common Mode Rejection Ratio).

[Image of Instrumentation Amplifier Circuit]

17. Frequency Compensation​

Frequency compensation is the business of preventing oscillation with negative feedback. When using an op-amp, you apply negative feedback to stabilize the system, but if you apply too much or ignore phase shifts, the signal can loop back and turn the feedback positive. This causes the op-amp to become unstable and oscillate.

The Problem (Phase Shift)​

  • As frequency increases, your gain decreases when approaching the stopband.
  • In multistage amplifiers, that 6dB roll-off (per octave) that occurs can become much steeper.
  • Remember that your phase shift increases at higher frequencies.
  • The Danger Zone: You will oscillate at 180° phase shift.
  • The Goal: To be stable, your open loop phase shift should be less than 180° at a given frequency (specifically, at the frequency where Loop Gain = 1).

Stability Analysis Fundamentals​

To determine stability, you must look at the total phase shift of the system: Op-Amp Phase Shift (-90° typically) + Feedback Network Phase Shift.

Phase Margin: The amount of phase "buffer" you have before you reach that instability point (180°) is called your Phase Margin.

  • Measurement: It is measured graphically at the point where your Unity Gain (Open Loop) and Closed Loop Gain curves meet. This intersection is called the Crossover Frequency.
  • Ideally: Op-amps typically have a phase output of -90°, giving a comfortable 90° phase margin.

Rate of Closure Method: A method to analyze stability by comparing the slopes of the Open Loop Gain and Closed Loop Gain graphs.

  • Formula: The frequency where these slope changes occur is determined by:

    F = 1 / (2 π R C)

Poles vs. Zeros (The Stability tug-of-war)​

1. Poles (The Destabilizers)

  • Effect: A Pole causes a -20dB/decade slope change and a -90° phase change.
  • Result: This pushes you closer to instability.
  • Physical Location (Feedback Path):
    • A capacitor shunted to ground from the output.
    • A capacitor in series with the non-inverting input.
  • Mechanism: These capacitors DELAY the feedback signal, causing a lag (phase shift) towards instability.

2. Zeros (The Stabilizers)

  • Effect: A Zero causes a +20dB/decade slope change and a +90° phase change.
  • Result: This pushes you towards stability.
  • Physical Location (Feedback Path):
    • A capacitor in the feedback path, typically going from the output to the inverting input.
  • Signal Path Note: Note that all of this logic is flipped when speaking with respect to the signal path vs. the feedback path.

Optimizing Phase Margin​

Where you place the pole determines your stability safety net:

  • The Intercept (45° Margin): Designing it so your pole occurs exactly at the intercept of the Closed Loop Gain and Open Loop Gain (with respect to frequency) gives you the biggest bandwidth, but your Phase Margin is only 45° (90° OpAmp - 45° Pole). This is often considered the minimum acceptable stability.
  • Before the Intercept (60° Margin): Keeping the pole slightly before the intercept frequency gives you a 60° Phase Margin. This is a common design target for robust systems.

Transient Response (The Time Domain Check)​

While Phase Margin is a frequency-domain tool, Transient Response is how you check stability in the time domain.

  • Definition: How the output responds to an abrupt input signal (like a Step or Square wave).
  • The Symptom: As you get less and less phase margin, your transient response gets worse. You will start seeing hard oscillations ("ringing") before the signal settles.

Practical Instability: Capacitive Loads​

A very common instability cause is driving a capacitive load (like an ADC input or a long cable).

  • The Problem: The output impedance of the op-amp reacts with the load capacitance. This creates a Pole in the feedback loop.
  • The Result: This pole adds phase lag, leading you closer to instability.
  • The Fix: You need to add a Zero to the feedback network at the correct frequency (specifically, before the crossover frequency happens). This cancels the phase lag of the pole.

The Solution (Dominant Pole Compensation)​

Using a follower as an example:

  1. You want to maintain stability for all frequencies in which gain is > 1.
  2. The easiest way to do this is adding enough load capacitance to the circuit so that the open loop gain drops to unity at about that 3dB frequency (close to the stopband).
  3. Phase Behavior: In this case, the open loop phase shift will stay at 90° and move towards 180° only when gain approaches unity.

Without Compensation: Without this capacitance compensation, the open loop gain drops first at 6dB/s (slope 1) then to 12dB/s (slope 2), resulting in 180° phase shifts while gain is still high. -> Oscillation.

With Compensation: By moving the first roll off down in frequency using the capacitance (Dominant Pole), then the roll off is controlled.

  • You stay at 90° phase shift for most of the pass band.
  • Trade-off: You are sacrificing Open Loop Gain (and Bandwidth) for Stability.
Non-Follower Applications

For non-follower op-amp situations (where you have High Closed Loop Gain), you don't have to put the pole at a very low frequency. This is because there is usually lower loop gain involved, so the curve crosses unity gain before the phase shift gets bad.

Next Steps

"Study up on compensators for more information" If you need to fix a specific oscillation, look up:

  • Lead Compensation: Adds phase lead to cancel lag.
  • Lag Compensation: Lowers gain at high frequencies.
  • Bode Plots: The graphical tool used to visualize this "Gain vs Phase" relationship.

18. Interfacing with SAR ADCs​

A specific challenge in modern design is driving Successive Approximation Register (SAR) ADCs. Unlike high-impedance inputs, SAR ADCs present a dynamic, switching load to the op-amp.

1. The Problem: Transient Currents ("Kickback")​

  • Mechanism: SAR ADCs use an internal Sample-and-Hold capacitor (CSH). When the ADC transitions from "Hold" to "Track," the switch closes.
  • The Glitch: Because CSH is often at a different voltage (e.g., Reset Voltage) than the input, a sudden Transient Current surge flows to equalize them.
  • Impact: This causes a voltage dip or "glitch" at the op-amp input. If the op-amp cannot settle this glitch before the acquisition phase ends, the sample is corrupted, degrading accuracy.

Image Source: Analog Devices

2. SAR Internals & Glitch Mechanics​

To understand the glitch, you must understand the internal components of the ADC front end.

Key Components:

  • Sampling Capacitor (CSH): Represents the ADC's internal capacitive DAC. It acquires and samples the input voltage (VADCIN).
  • Sample and Hold Switch (SWSH): Manages the transition between tracking and sampling phases.
  • Reset Switch (SWRST): Forces CSH to a specific voltage (VRST) between phases. It is never closed at the same time as SWSH.
  • Reset Voltage (VRST): The voltage CSH is discharged/recharged to. The difference between this and your signal determines how much charge the Op-Amp must replenish.

The Anatomy of a Glitch:

  1. Hold Phase: The Reset Switch closes, charging CSH to VRST.
  2. The Delta: A voltage difference (ΔV) exists between the Reset Voltage and your actual Input Voltage.
  3. Track Phase (The Kick): SWSH closes. The charge difference causes a sudden voltage glitch at the input pin.
  4. Sampling: The final voltage (VSH) is sampled at the rising edge of the next clock pulse.

Consequences: If the Analog Front End (AFE) is not fast enough to settle this input glitch before the next sample is taken:

  • You get measurement errors (accumulated errors or repeated failures).
  • Accuracy is lost.
  • Harmonic Distortion appears on the FFT plot.

3. The Output Capacitor Trap (The "Inductive" Op-Amp)​

To absorb this current spike, your instinct might be to place a large capacitor directly on the op-amp output to act as a "charge bucket."

  • The Physics: The output impedance (Zout) of an op-amp is a function of its Open Loop Gain. As frequency increases, Open Loop Gain drops, causing Zout to rise.
  • The Inductor Effect: This rising impedance with frequency behaves mathematically like an Inductor.
  • The Result: Connecting a capacitor (C) directly to this "Inductor" creates an LC Resonant Circuit. Instead of stabilizing the voltage, you create an oscillator (instability/ringing).

4. The Solution: R-C Isolation​

You must isolate the op-amp from the load capacitor using a series resistor (Riso).

  • Mechanism: The resistor becomes the dominant resistance. It "de-Qs" (dampens) the LC resonance, preventing oscillation.
  • Pole Management: It ensures the capacitor does not interact directly with the op-amp's feedback loop to create a destabilizing pole.

Image Source: TI Precision Labs

5. Selecting Components (The Trade-offs)​

Capacitor Selection (Cext): The external capacitor acts as a "Charge Reservoir" to refill the internal CSH instantly.

  • Too Small (e.g., 100pF): Insufficient charge. The op-amp must supply the current, leading to ringing and poor settling.
  • Too Large (e.g., 1μF): Excellent transient damping, BUT:
    • Requires a very small Riso to maintain bandwidth.
    • Small Riso reduces the damping effect, risking oscillation again.
    • Increased power dissipation due to higher peak currents.

Op-Amp Bandwidth Strategy:

  • Higher Bandwidth Op-Amp: Correlates with lower Open Loop Output Impedance (Zout) at high frequencies.
  • Benefit: Lower Zout means less "Inductance," requiring less aggressive damping.
  • Result: You can use a smaller Riso, which reduces the RC time constant, allowing the glitch to settle faster.

6. The Design Rule: Ratio-Based Selection​

Datasheets often overestimate requirements. A better approach is matching the external cap to the internal ADC physics.

  1. Identify Variables: Find CSH (Internal Sampling Cap) and your target error (e.g., < 1/2 LSB or < 100mV glitch).
  2. The Ratio Rule: Use the ratio of External Cap (Cext) to Internal Cap (CSH) to control the initial voltage drop.
    • 20 × CSH: Limits glitch to ~5%.
    • 100 × CSH: Limits glitch to ~1%.
  3. Goal: Aim for a kickback glitch of < 100mV. This keeps the disturbance within the op-amp's "Small Signal" bandwidth, allowing it to recover much faster than if it hit Slew Rate limits.

20. Signal Chain Noise & Design​

1. Signal Chain Noise Sources​

Quantization Noise: ADCs have finite steps. They must take an exact analog voltage and round it to the nearest digital code.

  • Definition: The difference between the actual input voltage and the digital representation.
  • Nature: It acts as the noise floor of the converter. There will always be quantization noise.
  • Resolution Rule:
    • Low Resolution (12-14 bits): Quantization noise dominates. The "steps" are large, so variance is high.
    • High Resolution (+16 bits): Thermal noise dominates. Performance degrades with temperature.

Clock Jitter:

  • Definition: The timing difference between when the clock signal actually arrived vs when it was supposed to arrive.
  • Impact: If your signal is fast and there is jitter, you sample the wrong voltage (amplitude error caused by timing error).
  • High Frequency Limit: When digitizing high-frequency signals, SNR is often limited by the external Clock Source, not the ADC itself.

SNR & ENOB:

  • SNR: A datasheet spec that lumps everything together—quantization, thermal noise, and internal distortion—into a single performance metric.
  • ENOB: The "Effective Number of Bits" derived from the SNR.

2. The Bandwidth Dilemma​

There is a fundamental conflict in precision signal chains:

  • The Need for Speed: To let the ADC input settle (recover from the "kickback" glitch discussed in Section 18), your driver op-amp needs high bandwidth.
  • The Penalty: High bandwidth means you are amplifying noise over a huge frequency range (e.g., 100 MHz), even if your signal is slow (e.g., 100 kHz).

3. The "Folding" Problem (Aliasing)​

You might think that noise at 50 MHz doesn't matter if you are only measuring up to 100 kHz.

  • Aliasing: Unfortunately, the sampling process creates an aliasing effect.
  • The Fold: All that wideband noise from the op-amp doesn't disappear; it folds back (aliases) down into your baseband (0 to fNyquist).
  • Result: Your "quiet" low-frequency measurement gets polluted by high-frequency noise that has disguised itself as low-frequency noise.
  • The Nyquist Rule: To properly reconstruct your analog signal, you must sample at least 2x your highest frequency input. If broken, information is permanently lost.

4. The Digital Solution: Oversampling & Filtering​

Since analog "brick wall" filters are impossible to build without ruining settling time, we move the filtering to the digital domain.

Step A: Oversample Run the ADC much faster than required (e.g., 15 MHz sampling for a 100 kHz signal).

  • Benefit: This spreads the quantization noise over a wider spectrum, lowering the noise density floor.
  • Benefit: It pushes the Nyquist frequency extremely high, creating a huge gap between your signal and the alias point. This allows you to use a simple, cheap 1st-order analog RC filter to block super-high frequencies.

Step B: Digital Filtering Apply a sharp digital filter to the data stream.

  • Precision: Digital filters can have incredibly sharp "brick wall" roll-offs that are impossible to build with analog capacitors and resistors.
  • Noise Removal: This filter removes the high-frequency noise before it can permanently alias into your signal band.

Step C: Decimation (Cleaning Up) Oversampling creates too much data (e.g., 1 MSPS when you only need 10 kSPS).

  • Process: Once the noise is digitally removed, you simply throw away the redundant samples (e.g., keep 1 out of every 100).
  • Result: You end up with the exact low data rate you wanted, but with the high-frequency noise removed, all without building a complex analog board.

The "Free" Resolution Rule: Every time you double your sampling rate (oversample by 2×) and digitally filter, you theoretically gain 3 dB of SNR (or 0.5 bits of resolution).

  • Formula: SNRimprovement = 10 × log( fsample / (2 × fsignal) )
  • Practical Benefit: This allows you to trade speed for resolution. You can use a noisy, fast ADC to achieve the performance of a quiet, slow ADC.

5. Voltage References​

You can spend a lot of money on a low noise ADC, but it is only as precise as the reference voltage.

  • The Bottleneck: If you connect a noisy reference directly to a quiet ADC, the total noise is dominated by the reference.
  • The Fix: Theoretically, you want your voltage reference to be perfectly DC. You can try and reach this with a very aggressive low-pass filter on the reference pin to kill broadband noise.